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Unit 426 Periods Allocated

Fundamentals of Digital Circuits

Covers digital logic gates, truth tables, Boolean simplification, and sequential circuits like flip-flops.

Syllabus Competency Mappings

Level 4.1Competency Level

Analyzes basic digital logic gates in terms of their unique functionalities.

Key Topics:
  • Basic gates: NOT, AND, OR
  • Combinational: NAND, NOR, XOR, XNOR
  • Universal gates: NAND, NOR
Level 4.2Competency Level

Simplifies logic expressions using laws of Boolean algebra and Karnaugh maps.

Key Topics:
  • Postulates and theorems
  • Sum of Products (SOP) and Product of Sums (POS)
  • Karnaugh Maps (K-Maps)

A/L ICT Competency Study Guide

1. Digital Logic Gates

Logic gates are the physical building blocks of digital integrated circuits:

  • AND Gate: Output is 1 only if ALL inputs are 1 (F = A . B).
  • OR Gate: Output is 1 if AT LEAST ONE input is 1 (F = A + B).
  • NOT Gate: Inverts the input (F = A' or F = Ā).
  • XOR (Exclusive OR) Gate: Output is 1 if inputs are different (F = A ⊕ B).

2. Universal Gates

NAND and NOR gates are classified as universal gates because any basic logic function (NOT, AND, OR) can be constructed solely using them.

Example: NOT gate using a NAND gate: Connect both inputs of a 2-input NAND gate together. When the input is A, the NAND output is (A . A)' = A', which acts as a NOT gate.

3. Karnaugh Map (K-Map) Simplification

A Karnaugh Map is a graphical method used to simplify Boolean expressions (SOP form) without using algebraic laws.

K-Map Rules:

  • Use Gray Code ordering for the row/column coordinates (e.g., 00, 01, 11, 10). This ensures only one bit changes between adjacent cells.
  • Group adjacent 1s in sizes of powers of 2 (pairs of 2, quads of 4, octets of 8).
  • Make groups as large as possible to reduce variables, allowing overlapping of cells and wrapping around borders.

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